1. Field of the Invention
The present invention generally relates to the field of manufacturing integrated circuits and, more particularly, to a method for concurrently manufacturing a metal gate for a non-planar semiconductor device and a polysilicon resistor.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (fin FET) has been developed to replace planar MOS transistors. The three-dimensional structure of a fin FET increases the overlapping area between the gate and the fin structure of the silicon substrate, and accordingly, the channel region is more effectively controlled. The drain-induced barrier lowering (DIBL) effect and short channel effect is therefore reduced. The channel region is also longer under the same gate length, and thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be further controlled by adjusting the work function of the gate. Currently, in order to further increase the performances of non-planar transistors, metal gates are commonly used in place of the conventional polysilicon gates as control electrodes. Two processing approaches are mainly used to obtain metal gate structures: a gate first process or a gate last process.
Nowadays, since integrated circuits often include various kinds of semiconductor devices, such as non-planar transistors, diodes, e-fuses, polysilicon resistors and the like, these kinds of semiconductor devices need to be integrated and fabricated through the same series of processes. However, many unavoidable drawbacks usually appear during the integration process. For example, a metal gate electrode and a resistor are often formed through two different steps in conventional processes. Since the metal gate electrode is fabricated prior to the formation of the resistor, this implies a duality of processing steps that incurs unnecessary processing cost.
In another case, during processes for replacing a dummy gate electrode in a dummy gate structure with a metal gate electrode, a polishing process is often carried out to remove entire hard masks in the dummy gate structure. The ability to control the-end point of the polishing process is critical since this end-point determines the height of the subsequently formed metal gate electrode and is therefore related to the performances of the non-planar transistor. Unfortunately, the height of the gate structure is often seriously reduced during this polishing process.
In order to overcome the above-mentioned drawbacks, a method for concurrently fabricating a metal gate and a polysilicon resistor in a non-planar semiconductor device is still needed.